Higher levels of integration for dynamic random access memories (DRAMs) are generally achieved by reducing the size of each memory cell. Accordingly, the space available for each memory cell capacitor is reduced, and the smaller memory cell capacitors may have reduced capacitance. A lower capacitance for a memory cell capacitor may increase the difficulty of low voltage operation, and a smaller capacitance may also increase soft error rates. Furthermore, a lower memory cell capacitance may result in higher levels of difficulty reading data from the memory cell.
Accordingly, there is a need in the art to provide relatively small memory cell capacitors which provide relatively high capacitances. In particular, memory cell capacitances have been increased by increasing the surface areas of the storage electrode such as by forming three-dimensional storage electrodes. For example, mesa-shaped capacitor storage electrodes have been used because the side walls of the mesa provide an increase in the surface area of the storage electrode. The surface area of the storage electrode is thus dependent on the height of the mesa. Capacitor structures are discussed, for example, in U.S. Pat. No. 5,330,614 to Ahn, the disclosure of which is hereby incorporated herein in its entirety by reference.
FIGS. 1 through 5 are cross-sectional views illustrating steps of a method for manufacturing a capacitor having a mesa-shaped storage electrode for an integrated circuit memory device according to the prior art. As shown in FIG. 1, a field oxide 110 defines active and non-active regions of the substrate 101. The memory cell access transistors are formed on the active region of the substrate, and each of these transistors includes source/drain regions 111 and 112, and a gate electrode 113. A buried bit line 114 is formed in the insulating layer 120, and this buried bit line 114 is connected to the source/drain region 112 of a memory cell access transistor. The insulating layer 120 serves as a planarization layer, and the etching stop layer 125 is formed on the insulating layer 120. In particular, the insulating layer 120 can be a layer of borophosphosilicate glass (BPSG), and the etching stop layer 125 can be a layer of silicon nitride (Si.sub.3 N.sub.4).
Contact holes 130 are formed in the etch stop layer 125 and the insulating layer 120 thereby exposing source/drain regions 111 of the memory cell access transistors. The contact holes can be formed using photolithography and etch steps. A conductive layer is formed on the etch stop layer 125, and this conductive layer fills the contact holes 130 thereby providing electrical contact with the source/drain regions 111. The conductive layer 140 can be a layer of doped polycrystalline silicon. A photoresist pattern 150 is then formed on the conductive layer 140 opposite the contact holes 130. In particular, the photoresist pattern 150 can be formed by coating a layer of photoresist on the conductive layer 140 and then patterning it using a photolithography step.
The conductive layer 140 is then patterned by etching using the photoresist pattern 150 as a mask. Accordingly, mesa-shaped storage electrodes 140a are formed on the etch stop layer 125, and each of these mesa-shaped storage electrodes is electrically connected to a respective source/drain region 111. The etch stop layer 125 can be used to reduce undercutting of the mesa-shaped storage electrode 140a. As shown in FIG. 4, the photoresist pattern is then removed.
A dielectric layer 180 and a plate electrode 190 are then formed on the mesa-shaped storage electrodes 140a as shown in FIG. 5. Accordingly, a plurality of memory cell capacitors can be formed wherein each of the capacitors includes a mesa-shaped storage electrode. More particularly, the dielectric layer 180 can include an oxide/nitride/oxide (ONO) layer, and the plate electrode 190 can be formed by depositing a layer of doped polycrystalline silicon on the dielectric layer.
Accordingly, each of the memory cell capacitors of FIG. 5 has a respective capacitance proportional to the surface area of the storage electrode 140a. This surface area is equal to the sum of the area of the upper surface of the electrode 140a and the sidewalls of the electrode 140a. The surface area of the electrode 140a can thus be increased without increasing the surface area occupied by the electrode by increasing the thickness of the storage electrode thereby increasing the sidewalls thereof. By increasing the thickness of the storage electrode, the capacitance of the capacitor including the storage electrode can be increased without increasing the surface area occupied by the capacitor.
According to the method discussed above, the thickness of the storage electrode 140a can be increased to increase a capacitance for the capacitor without increasing a surface area for the capacitor. The increased thickness of the storage electrode 140a, however, may also increase a step difference between a cell array region of the memory device where the storage electrodes are formed and a peripheral circuit region not having storage electrodes. Accordingly, focus margins may be reduced for subsequent photolithography steps, and irregular reflections may also be generated. The reliability of subsequently formed metal wiring may thus be reduced. It may thus be more difficult to form metal wiring patterns on memory devices formed as discussed above.